Designing with the Zynq UltraScale+ RFSoC
1. Course Description
Provides an overview of the hard block capabilities for the Zynq UltraScale+ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.
2. Duration
2 DAYs
3. Software Tools
Vivado® Design Suite and SDx
4. Prerequisites
Basic knowledge of comunication， mathematics, matix and complex function.
Program knowledge about C/C++, HDL.
5. Course Outline
- Describing the RFSoC family in general
- Identifying applications for the Data Converter and SD-FEC blocks
- Configuring, simulating, and implementing the blocks
- Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes
- Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device
|
